Microsoft Corporation - Senior Engineer, Mask Layout
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.
As Microsoft's cloud business continues to grow, the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Semi and Custom IP team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with customer-focused solutions, and insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Senior Engineer, Mask Layout to join the team.
Responsibilities:
- Lead the design and development of custom memory layouts: Oversee the entire layout design process from conceptualization to final tape-out. Work closely with circuit designers to understand the specific requirements and constraints for each project. Develop layout strategies that optimize for performance, area, and power consumption. Ensure designs meet or exceed specifications and adhere to industry standards and best practices.
- Work closely within our global teams, including circuit designers, process engineers, and verification teams, to ensure seamless integration and high-quality deliverables.
- Conduct layout reviews and provide feedback to ensure adherence to design rules and best practices.
- Optimize layout designs for manufacturing, reliability, and yield.
- Mentor and guide other layout engineers, providing technical expertise and support.
- Stay updated on the latest industry trends and advancements in memory technology.
Qualifications:
Required Qualifications:
- 7+ years of related technical engineering experience
- OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
- OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
- OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- 5+ years of experience in custom memory layout design, with a focus on SRAM.
- 5+ years of experience using Calibre and Cadence tools.
Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Preferred Qualifications:
- Experience with using and setting up Ansys Totem.
- Deep knowledge of custom digital layout design.
- Understanding of analog/mixed-signal layout (AMS).
- Expertise in Python, SKILL, or TCL scripting and C programming.
- Excellent problem-solving skills and creative thinking.
- Proficiency with 5nm and/or 3nm technology nodes.
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $153,600 - $250,200 per year.
Microsoft will accept applications for the role until October 17, 2024.
Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html).
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